Integrated circuit and method of fabricating the same

ABSTRACT

A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a divisional of U.S. patent application Ser. No. 15/145,354, filed on May 3, 2016, and entitled “Integrated Circuit and Method of Fabricating the Same,” which application is incorporated herein by reference.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation.

The trend in very-large-scale integration (VLSI) technology has resulted in narrower interconnection lines and smaller contacts. Furthermore, integrated circuit designs are becoming more complex and denser. More devices are compressed in integrated circuits to improve performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a top view of a cell layout in accordance with some embodiments of the disclosure.

FIG. 2 is a top view of a layout in accordance with some embodiments of the disclosure.

FIG. 3 is a schematic diagram of an inverter in accordance with some embodiments of the disclosure.

FIG. 4 is a top view of a layout in accordance with some embodiments of the present disclosure.

FIG. 5A to FIG. 5C are top views of cell layouts in accordance with different embodiments of the disclosure.

FIG. 6 is a layout in accordance with some embodiments of the disclosure.

FIG. 7 is a flowchart of a method of configuring an integrated circuit layout in accordance with some embodiments of the disclosure.

FIG. 8 is a processing system to generate one or more of the above described layout embodiments in accordance with some embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Reference is made to FIG. 1, in which FIG. 1 is a top view of a cell layout in accordance with some embodiments of the present disclosure. The cell 100 is present on a semiconductor substrate. The cell 100 has a cell boundary including a top edge 212, a bottom edge 214, and opposite side edges 216 and 218. A cell height H is defined between the top edge 212 and the bottom edge 214. A cell width W is defined between the opposite side edges 216 and 218.

The cell 100 includes a first transistor region 112 and a second transistor region 114, in which the first transistor region 112 is arranged vertically next to the second transistor region 114. A common boundary line 215 separates the first transistor region 112 and the second transistor region 114. The first transistor region 112 of the cell 100 can be arranged to form PMOS (P-channel Metal Oxide Semiconductor) transistors and can be regarded as a PMOS region 112. The second transistor region 114 of the cell 100 can be arranged to form NMOS (N-channel Metal Oxide Semiconductor) transistors and can be regarded as an NMOS region 114.

A plurality of P-type active regions 120 a-120 d are present in the PMOS region 112, and a plurality of N-type active regions 124 a-124 d are present in the NMOS region 114. In some embodiments, an active region, such as the P-type active regions 120 a-120 d and the N-type active regions 124 a-124 d, is also referred to herein as OD (oxide-dimensioned region). In FIG. 1, the P-type active regions 120 a-120 d are substantially perpendicular to the top edge 212 and are substantially equally spaced apart. The N-type active regions 124 a-124 d are substantially perpendicular to the bottom edge 214 and are substantially equally spaced apart. In some embodiments, the P-type active regions 120 a-120 d and the N-type active regions 124 a-124 d are fin shaped, and the P-type active regions 120 a-120 d and the N-type active regions 124 a-124 d are substantially parallel to each other and are staggered in the PMOS region 112 and the NMOS region 114.

Gate electrodes 150 a-150 d and dummy gate electrodes 130 a-130 c are present over the semiconductor substrate. In FIG. 1, the gate electrodes 150 a-150 d and the dummy gate electrodes 130 a-130 c are substantially parallel to each other and are substantially parallel to the top edge 212, the common boundary line 215, and the bottom edge 214. The gate electrodes 150 a-150 d and the dummy gate electrodes 130 a-130 c are formed of polysilicon or other electrically conductive materials such as metals, metal alloys, and metal silicides. The dummy gate electrodes 130 a-130 c are arranged to not act as a gate to any transistor. In some embodiments, gate electrodes and dummy gate electrodes, such as the gate electrodes 150 a-150 d and the dummy gate electrodes 130 a-130 c, are also referred to herein as PO. In some embodiments, the dummy gate electrodes 130 a-130 c are also referred to herein as PODE (poly on OD edge).

The gate electrodes 150 a and 150 b are present in the PMOS region 112. The gate electrode 150 a crosses the P-type active regions 120 a and 120 c and is partially present on an edge of the P-type active region 120 b, in which the gate electrode 150 a is regarded as a dummy gate electrode to the P-type active region 120 b. The gate electrode 150 b crosses the P-type active regions 120 b and 120 d and is partially present on an edge of the P-type active region 120 c, in which the gate electrode 150 b is regarded as a dummy gate electrode to the P-type active region 120 c. The gate electrodes 150 c and 150 d are present in the NMOS region 114. The gate electrode 150 c crosses the N-type active regions 124 a and 124 c and is partially present on an edge of the N-type active region 124 b, in which the gate electrode 150 c is regarded as a dummy gate electrode to the N-type active region 124 b. The gate electrode 150 d crosses the N-type active regions 124 b and 124 d and is partially present on an edge of the N-type active region 124 c, in which the gate electrode 150 d is regarded as a dummy gate electrode to the N-type active region 124 c.

The cell 100 further includes a plurality of cutting patterns 160 a-160 d, such as cut polysilicon (CPO) patterns, for respectively terminating the gate electrodes 150 a-150 d. The cutting patterns 160 a-160 d respectively represent cut sections or patterning areas where the gate electrodes 150 a-150 d are removed. In some embodiments, the length of at least one of the gate electrodes 150 a-150 d is less than the length of at least one of the dummy gate electrodes 130 a-130 c because of existence of the cutting patterns 160 a-160 d.

In some embodiments, the gate electrodes 150 a-150 d are staggered in the cell 100. As shown in FIG. 1, the gate electrodes 150 a and 150 c extend from the side edge 216 while being spaced from the side edge 218 respectively by the cutting patterns 160 a and 160 c, and the gate electrodes 150 b and 150 d extend from the side edge 218 while being spaced from the side edge 216 respectively by the cutting patterns 160 b and 160 d.

In some embodiments, the dummy gate electrode 130 a is present on the top edge 212, the dummy gate electrode 130 b is present on the common boundary line 215, and the dummy gate electrode 130 c is present on the bottom edge 214. The gate electrodes 150 a and 150 b are present between the dummy gate electrodes 130 a and 130 b, in which the gate electrode 150 a is present between the dummy gate electrode 130 a and the gate electrode 150 b, and the gate electrode 150 b is present between the gate electrode 150 a and the dummy gate electrode 130 b. The gate electrodes 150 c and 150 d are present between the dummy gate electrodes 130 b and 130 c, in which the gate electrode 150 c is present between the dummy gate electrode 130 b and the gate electrode 150 d, and the gate electrode 150 d is present between the gate electrode 150 c and the dummy gate electrode 130 c.

In some embodiments, the P-type active regions 120 a-120 d are staggered in the PMOS region 112, and the N-type active regions 124 a-124 d are staggered in the NMOS region 114. As shown in FIG. 1, the P-type active regions 120 a and 120 c are partially present under the dummy gate electrode 130 a while being spaced from the dummy gate electrode 130 b. The P-type active regions 120 b and 120 d are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 a. The N-type active regions 124 a and 124 c are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 c. The N-type active regions 124 b and 124 d are partially present under the dummy gate electrode 130 c while being spaced from the dummy gate electrode 130 b.

Reference is made to FIG. 2, in which FIG. 2 is a top view of a layout in accordance with some embodiments of the present disclosure. The layout includes a plurality of the cells 100 abutted in at least one row. The cell heights H of the cells 100 are substantially the same, which enables the cells 100 to be placed in the row. The dummy gate electrodes 130 a-130 c extend substantially along a longitudinal direction of the row. Therefore, the lengths of the dummy gate electrodes 130 a-130 c are not constrained by the cell heights H of the cells 100.

In some embodiments, the dummy gate electrodes 130 a-130 c are continuous at least between corresponding active regions of adjacent cells 100. As shown in FIG. 2, the dummy gate electrodes 130 a-130 c of adjacent cells 100 at the same horizontal level are monolithically connected to each other. For example, the dummy gate electrodes 130 a of adjacent cells 100 are monolithically connected to each other, the dummy gate electrodes 130 b of adjacent cells 100 are monolithically connected to each other, and the dummy gate electrodes 130 c of adjacent cells 100 are monolithically connected to each other. As a result, the dummy gate electrodes 130 a-130 c can be regarded as continuous conductive lines across the cells 100, and the lengths of the dummy gate electrodes 130 a-130 c can be as long as a sum of the cell widths W of the cells 100, respectively.

As shown in FIG. 2, the dummy gate electrodes 130 a-130 c are continuous across at least one common boundary of adjacent cells 100. Since the cutting patterns 160 respectively terminate the gate electrodes 150, the length of at least one of the dummy gate electrodes 130 a-130 c is greater than the length of at least one of the gate electrodes 150, in which the length of each gate electrode 150 is a distance between the corresponding cutting patterns 160.

In some embodiments, the dummy gate electrodes 130 a-130 c extend at least across two adjacent cells 100 abutted in the row. As shown in FIG. 2, the cutting patterns 160 are respectively present between end-to-end adjacent gate electrodes 150, and therefore the length of at least one of the dummy gate electrodes 130 a-130 c is greater than at least a sum of lengths of two end-to-end adjacent gate electrodes 150.

Since the dummy gate electrodes 130 a-130 c are continuous and electrically conductive, the dummy gate electrodes 130 a-130 c can be utilized for interconnecting the cells 100. That is, some signals may travel through the dummy gate electrodes 130 a-130 c rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells 100 can be reduced. Furthermore, a pitch between adjacent cells 100 can be reduced as well since the amount of the metal one lines and/or the metal two lines for interconnecting the cells 100 is reduced.

Reference is made to FIG. 3, which is a schematic diagram of an inverter in accordance with some embodiments of the present disclosure. The inverter 300 includes a PMOS transistor 310 and an NMOS transistor 320. An input port 330 of the inverter 300 is electrically connected to gate terminals of the PMOS transistor 310 and the NMOS transistor 320. An output port 340 of the inverter 300 is electrically connected to drain terminals of the PMOS transistor 310 and the NMOS transistor 320.

When the input port 330 is set to “0” (for example, ground voltage), the PMOS transistor 310 is turned on, and the NMOS transistor 320 is turned off. In such a situation, current flows from VDD (voltage drain drain) through the PMOS transistor 310 to the output port 340. When the input port 330 is set to “1” (for example, operation voltage), the PMOS transistor 310 is turned off, and the NMOS transistor 320 is turned on. In such a situation, current flows from the output port 340 through the NMOS transistor 320 to VSS (voltage source source).

FIG. 4 is a top view of a layout in accordance with some embodiments of the present disclosure. The PMOS region 112 of the cell 100 includes four PMOS transistors, such as the PMOS transistor 310 in FIG. 3. Source regions 121 a-121 d and drain regions 123 a-123 d are respectively present in the P-type active regions 120 a-120 d. Each of adjacent source regions 121 a-121 d and drain regions 123 a-123 d are on opposite sides of a corresponding gate electrode. In such a situation, each of the adjacent source regions 121 a-121 d, the drain regions 123 a-123 d, and a corresponding gate electrode form a PMOS transistor. For example, the source region 121 a, the drain region 123 a, and the gate electrode 150 a form a first PMOS transistor. For another example, the source region 121 b, the drain region 123 b, and the gate electrode 150 b form a second PMOS transistor. For yet another example, the source region 121 c, the drain region 123 c, and the gate electrode 150 a form a third PMOS transistor. For still another example, the source region 121 d, the drain region 123 d, and the gate electrode 150 b form a fourth PMOS transistor.

The NMOS region 114 of the cell 100 includes four NMOS transistors, such as the NMOS transistor 320 in FIG. 3. Drain regions 125 a-125 d and source regions 126 a-126 d are respectively present in the N-type active regions 124 a-124 d. Each of adjacent drain regions 125 a-125 d and source regions 126 a-126 d are on opposite sides of a corresponding gate electrode. In such a situation, each of the adjacent drain regions 125 a-125 d, the source regions 126 a-126 d, and a corresponding gate electrode form an NMOS transistor. For example, the drain region 125 a, the source region 126 a, and the gate electrode 150 c form a first NMOS transistor. For another example, the drain region 125 b, the source region 126 b, and the gate electrode 150 d form a second NMOS transistor. For yet another example, the drain region 125 c, the source region 126 c, and the gate electrode 150 c form a third NMOS transistor. For still another example, the drain region 125 d, the source region 126 d, and the gate electrode 150 d form a fourth NMOS transistor.

A VDD power supply line 350 and a VSS ground line 360 are implemented, for example, in metal two lines. In a top-down sequence, the VDD power supply line 350 is connected through conductive via ones 382 a, conductive metal one lines 370 a, and conductive via zeros 380 a to each of the source regions 121 a-121 d of the corresponding PMOS transistors. Similarly, the VSS ground line 360 is connected through conductive via ones 382 b, conductive metal one lines 370 b, and conductive via zeros 380 b to each of the source regions 126 a-126 d of the corresponding NMOS transistors. The drain regions 123 a-123 d of the PMOS transistors are respectively connected to the drain regions 125 a-125 d of the NMOS transistors through conductive via zeros 380 c and conductive metal one lines 370 c.

In some embodiments where the cell 100 is arranged to form two inverters, output ports of the two inverters are respectively on at least two output metal lines (not shown). One of the output metal lines is electrically connected to each of the drain regions 123 a and 123 c of the PMOS transistors and the drain regions 125 a and 125 c of the NMOS transistors, and another of the output metal lines is electrically connected to each of the drain regions 123 b and 123 d of the PMOS transistors and the drain regions 125 b and 125 d of the NMOS transistors. On the other hand, input ports of the two inverters are respectively on two input metal lines (not shown). One of the input metal lines is electrically connected to each of the gate electrodes 150 a and 150 c, and another of the input metal lines is electrically connected to each of the gate electrodes 150 b and 150 d. As a result, the two inverters can be formed within the cell 100.

Reference is made to FIG. 5A to FIG. 5C, which are top views of cell layouts in accordance with some embodiments of the present disclosure. The difference among FIGS. 5A-5C and FIG. 1 includes the arrangement of the P-type active regions 120 a-120 d, the N-type active regions 124 a-124 d, and the gate electrodes 150 a-150 d. Referring to FIG. 5A, the P-type active regions 120 b and 120 d are partially present under the dummy gate electrode 130 a while being spaced from the dummy gate electrode 130 b. The P-type active regions 120 a and 120 c are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 a. The N-type active regions 124 b and 124 d are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 c. The N-type active regions 124 a and 124 c are partially present under the dummy gate electrode 130 c while being spaced from the dummy gate electrode 130 b. The gate electrodes 150 a and 150 c extend from the side edge 218 while being spaced from the side edge 216 respectively by the cutting patterns 160 a and 160 c, and the gate electrodes 150 b and 150 d extend from the side edge 216 while being spaced from the side edge 218 respectively by the cutting patterns 160 b and 160 d.

Referring to FIG. 5B, the P-type active regions 120 a and 120 b are partially present under the dummy gate electrode 130 a while being spaced from the dummy gate electrode 130 b. The P-type active regions 120 c and 120 d are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 a. The N-type active regions 124 a and 124 b are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 c. The N-type active regions 124 c and 124 d are partially present under the dummy gate electrode 130 c while being spaced from the dummy gate electrode 130 b. The gate electrode 150 a crosses the P-type active regions 120 a and 120 b while not crossing the P-type active regions 120 c and 120 d. The gate electrode 150 b crosses the P-type active regions 120 c and 120 d while not crossing the P-type active regions 120 a and 120 b. The gate electrode 150 c crosses the N-type active regions 124 a and 124 b while not crossing the N-type active regions 124 c and 124 d. The gate electrode 150 d crosses the N-type active regions 124 c and 124 d while not crossing the N-type active regions 124 a and 124 b.

Referring to FIG. 5C, the P-type active regions 120 c and 120 d are partially present under the dummy gate electrode 130 a while being spaced from the dummy gate electrode 130 b. The P-type active regions 120 a and 120 b are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 a. The N-type active regions 124 c and 124 d are partially present under the dummy gate electrode 130 b while being spaced from the dummy gate electrode 130 c. The N-type active regions 124 a and 124 b are partially present under the dummy gate electrode 130 c while being spaced from the dummy gate electrode 130 b. The gate electrode 150 a crosses the P-type active regions 120 c and 120 d while not crossing the P-type active regions 120 a and 120 b. The gate electrode 150 b crosses the P-type active regions 120 a and 120 b while not crossing the P-type active regions 120 c and 120 d. The gate electrode 150 c crosses the N-type active regions 124 c and 124 d while not crossing the N-type active regions 124 a and 124 b. The gate electrode 150 d crosses the N-type active regions 124 a and 124 b while not crossing the N-type active regions 124 c and 124 d.

FIG. 6 is a top view of a layout in accordance with some embodiments of the present disclosure. The cell 400 includes a PMOS region 412 and an NMOS region 414, in which the NMOS region 414 is arranged horizontally next to the PMOS region 412. A plurality of P-type active regions 420 a-420 d are present in the PMOS region 412. The P-type active regions 420 a-420 d are substantially parallel to each other and are staggered in the PMOS region 412. The P-type active regions 420 a-420 d are substantially perpendicular to the top edge 402 of the cell 400.

A plurality of N-type active regions 424 a-424 d are present in the NMOS region 414. The N-type active regions 424 a-424 d are substantially parallel to each other and are staggered in the NMOS region 414. The N-type active regions 424 a-424 d are substantially perpendicular to the top edge 402 of the cell 400 as well.

The cell 400 includes a plurality of dummy gate electrodes 430 a and 430 b and a plurality of gate electrodes 440 a and 440 b. The dummy gate electrodes 430 a and 430 b are respectively present on the top edge 402 and the bottom edge 404 of the cell 400. The dummy gate electrode 430 a is partially present on edges of the P-type active regions 420 a and 420 c and the N-type active regions 424 a and 424 c. The dummy gate electrode 430 b is partially present on edges of the P-type active regions 420 b and 420 d and the N-type active regions 424 b and 424 d. The gate electrodes 440 a and 440 b are arranged between the dummy gate electrodes 430 a and 430 b. The gate electrodes 440 a and 440 b are substantially parallel to each other and are substantially parallel to the top edge 402.

The cell 400 further includes a plurality of cutting patterns 490 a and 490 b for respectively terminating the gate electrodes 440 a and 440 b. The gate electrode 440 a crosses the P-type active regions 420 a and 420 c and the N-type active regions 424 a and 424 c while not crossing the N-type active region 424 d because of existence of the cutting pattern 490 a. The gate electrode 440 b crosses the N-type active regions 424 b and 424 d and the P-type active regions 420 b and 420 d while not crossing the P-type active region 420 a because of existence of the cutting pattern 490 b.

In some embodiments, the gate electrodes 440 a is partially present on edges of the P-type active regions 420 b and 420 d and the N-type active region 424 b, and thus the gate electrode 440 a is regarded as a dummy gate electrode to each of the P-type active regions 420 b and 420 d and the N-type active regions 424 b. The gate electrode 440 b is partially present on edges of the P-type active region 420 c and the N-type active regions 424 a and 424 c, and thus the gate electrode 440 b is regarded as a dummy gate electrode to each of the P-type active region 420 c and the N-type active regions 424 a and 424 c.

Two VDD power supply lines 450 a and 450 b are implemented, for example, in metal two lines. The VDD power supply lines 450 a and 450 b are respectively arranged at opposite sides of the cell 400. Two VSS ground lines 460 a and 460 b are implemented, for example, in metal two lines. The VSS ground lines 460 a and 460 b are arranged at opposite sides of the cell 400 as well. In FIG. 6, the VDD power supply line 450 a is present between the VSS ground line 460 a and the top edge 402 of the cell 400, and the VDD power supply line 450 b is present between the bottom edge 404 of the cell 400 and the VDD ground line 460 b.

In a top-down sequence, the VDD power supply line 450 a is connected through conductive via ones 482 a, conductive metal one lines 470 a, and conductive via zeros 480 a to each of source regions in the P-type active regions 420 a and 420 c. The VDD power supply line 450 b is connected through conductive via ones 482 b, conductive metal one lines 470 b, and conductive via zeros 480 b to each of source regions in the P-type active regions 420 b and 420 d. The VSS ground line 460 a is connected through conductive via ones 482 c, conductive metal one lines 470 c, and conductive via zeros 480 c to each of source regions in the N-type active regions 424 a and 424 c. The VSS ground line 460 b is connected through conductive via ones 482 d, conductive metal one lines 470 d, and conductive via zeros 480 d to each of source regions in the N-type active regions 424 b and 424 d.

Drain regions in the P-type active regions 420 a-420 d are respectively connected to the corresponding drain regions in the N-type active regions 424 a-424 d through conductive metal one lines 470 e and conductive via zeros 480 e. As a result, the source region in the P-type active region 420 a is connected to the VDD power supply line 450 a, the drain region in the P-type active region 420 a is connected to the drain region in the N-type active region 424 a, and the source region in the N-type active region 424 a is connected to the VSS ground line 460 a. The source region in the P-type active region 420 c is connected to the VDD power supply line 450 a, the drain region in the P-type active region 420 c is connected to the drain region in N-type active region 424 c, and the source region in the N-type active region 424 c is connected to the VSS ground line 460 a. The P-type active regions 420 a and 420 c, and the N-type active regions 424 a and 424 c share the gate electrode 440 a, thus an inverter including the P-type active regions 420 a and 420 c, the N-type active regions 424 a and 424 c and the gate electrode 440 a is provided.

Similarly, the source region in the P-type active region 420 b is connected to the VDD power supply line 450 b, the drain region in the P-type active region 420 b is connected to the drain region in the N-type active region 424 b, and the source region in the N-type active region 424 b is connected to the VSS ground line 460 b. The source region in the P-type active region 420 d is connected to the VDD power supply line 450 b, the drain region in the P-type active region 420 d is connected to the drain region in the N-type active region 424 d, and the source region in the N-type active region 424 d is connected to the VSS ground line 460 b. The P-type active regions 420 b and 420 d and the N-type active regions 424 b and 424 d share the gate electrode 440 b, thus an inverter including the P-type active regions 420 b and 420 d, the N-type active regions 424 b and 424 d, and the gate electrode 440 b is provided.

Reference is made to FIG. 7, which is a flowchart of a method of configuring an integrated circuit layout in accordance with some embodiments of the disclosure. In the design of an integrated circuit, various cells having predetermined functions are used, and the layouts of cells are stored in, for example, at least one cell library. The method begins at operation 510, in which a plurality of cells are chosen from the cell library. The cells can be any of the cells described above. The method goes to operation 520, in which the cells are placed into one or more desired locations on an integrated circuit layout and are abutted in at least one row. At least one of the dummy gate electrodes of the cells are continuous across at least one common boundary between adjacent cells.

Reference is made to FIG. 8, which is a processing system 600 to generate one or more of the above described layout embodiments. Processing system 600 includes a processor 602, which may include a central processing unit, an input/output circuitry, a signal processing circuitry, and a volatile and/or a non-volatile memory. Processor 602 receives input, such as user input, from input device 604. The input device 604 may include one or more of a keyboard, a mouse, a tablet, a contact sensitive surface, a stylus, a microphone, and the like. The processor 602 may also receive input, such as standard cell layouts, cell libraries, models, and the like, from a non-transitory machine readable storage medium 608. The non-transitory machine readable storage medium may be located locally to the processor 602, or may be remote from the processor 602, in which communications between the processor 602 and the non-transitory machine readable storage medium 608 occur over a network, such as a telephone network, the Internet, a local area network, wide area network, or the like. The non-transitory machine readable storage medium 608 may include one or more of a hard disk, magnetic storage, optical storage, non-volatile memory storage, and the like. Included in the non-transitory machine readable storage medium 608 may be database software for organizing data and instructions stored on the non-transitory machine readable storage medium 608. The processing system 600 may include an output device 606, such as one or more of a display device, speaker, and the like for outputting information to a user. As described above, the processor 602 generates a layout for an integrated circuit. The layout may be stored in the non-transitory machine readable storage medium 608. One or more integrated circuit manufacturing machines, such as a photomask generator 610 may communicate with the non-transitory machine readable storage medium 608, either locally or over a network, either directly or via an intermediate processor such as processor 602. In some embodiments, the photomask generator 610 generates one or more photomasks to be used in the manufacture of an integrated circuit, in conformance with a layout stored in the non-transitory machine readable storage medium 608.

In some embodiments, at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

According to some embodiments of the disclosure, an integrated circuit includes a first cell and a second cell. The first cell includes at least one first active region and at least one first gate electrode crossing the first active region. The second cell includes at least one second active region and at least one second gate electrode crossing the second active region. The first gate electrode and the second gate electrode are arranged end-to-end. The integrated circuit further includes at least one dummy gate electrode partially present on edges of the first active region and the second active region. The dummy gate electrode is continuous at least between the first active region and the second active region.

According to some embodiments of the disclosure, an integrated circuit includes at least one first active region, at least one first gate electrode crossing the first active region, at least one second active region, at least one second gate electrode crossing the second active region, in which the second gate electrode is disconnected with the first gate electrode. The integrated circuit further includes at least one first dummy gate electrode partially present on edges of the first active region and the second active region, in which a length of the first dummy gate electrode is greater than a length of the first gate electrode.

According to some embodiments, a method of configuring an integrated circuit layout using a processor includes using the processor, choosing a plurality of cells from a cell library; using the processor, placing the cells on the integrated circuit layout, wherein the placing the cells forms at least one continuous PODE (poly on OD edge) on the integrated circuit layout, and the continuous PODE extends across at least one common boundary between the cells; generating a set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout; and storing the set of instructions in an non-transitory machine readable storage medium.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method of forming an integrated circuit, the method comprising: forming a first cell, wherein forming the first cell comprises: forming a first active region; and forming a first gate electrode over the first active region; forming a second cell, wherein forming the second cell comprises: forming a second active region; and forming a second gate electrode over the second active region, wherein the first gate electrode and the second gate electrode are aligned along a same line and are separated from each other; and forming a first dummy gate electrode that extends continuously along a first edge of the first cell and along a first edge of the second cell, wherein in a top view, the first dummy gate electrode overlaps with a first end of the first active region and overlaps with a first end of the second active region.
 2. The method of claim 1, wherein forming the first cell further comprises forming a third active region in the first cell, the third active region being parallel to the first active region, wherein in the top view, the first active region and the third active region are staggered.
 3. The method of claim 2, wherein forming the first cell further comprises forming a third gate electrode in the first cell over the third active region, the third gate electrode being parallel to the first gate electrode, wherein in the top view, the first gate electrode and the third gate electrode are staggered.
 4. The method of claim 1, wherein forming the first dummy gate electrode comprises forming the first dummy gate electrode using an electrically conductive material.
 5. The method of claim 1, wherein the first cell and the second cell have a same cell height, wherein the first cell and the second cell are formed immediately adjacent to each other and aligned in a row.
 6. The method of claim 5, wherein the first active region of the first cell is formed in a PMOS region of the first cell, and the second active region of the second cell is formed in a PMOS region of the second cell, wherein the first active region and the second active region are aligned in a longitudinal direction of the row.
 7. The method of claim 6, wherein forming the first cell further comprises forming a third active region in an NMOS region of the first cell, wherein the first active region and the third active region are aligned along a same line.
 8. The method of claim 7, wherein the method further comprises forming a second dummy gate electrode between the PMOS region of the first cell and the NMOS region of the first cell.
 9. The method of claim 8, wherein the method further comprises forming a third dummy gate electrode along a second edge of the first cell opposing the first edge of the first cell, wherein the second dummy gate electrode is between the first dummy gate electrode and the third dummy gate electrode.
 10. The method of claim 5, wherein the first dummy gate electrode extends along a longitudinal direction of the row.
 11. The method of claim 10, wherein a length of the first dummy gate electrode, measured along the longitudinal direction of the row, is larger than a sum of a first length of the first gate electrode and a second length of the second gate electrode, wherein the first length and the second length are measured along the longitudinal direction of the row.
 12. The method of claim 1, further comprising forming a second dummy gate electrode along a second edge of the first cell opposing the first edge of the first cell, and along a second edge of the second cell opposing the first edge of the second cell.
 13. A method of forming an integrated circuit, the method comprising: forming a first p-type active region; forming a first gate electrode across the first p-type active region; forming a first n-type active region, the first n-type active region being parallel to the first p-type active region; forming a second gate electrode across the first n-type active region, the second gate electrode being parallel with the first gate electrode, the second gate electrode being spaced apart from the first gate electrode; and forming a first dummy gate electrode between the first p-type active region and the first n-type active region, the first dummy gate electrode extending in parallel with the first gate electrode.
 14. The method of claim 13, wherein in a top view, the first dummy gate electrode overlaps at least partially with a first end of the first p-type active region and overlaps at least partially with a first end of the first n-type active region.
 15. The method of claim 13, wherein a length of the first dummy gate electrode is greater than a length of the first gate electrode and greater than a length of the second gate electrode.
 16. The method of claim 13, further comprising; forming a second p-type active region on a same side of the first dummy gate electrode as the first p-type active region, the second p-type active region being parallel with the first p-type active region; and forming a third gate electrode across the second p-type active region, the third gate electrode being parallel to the first gate electrode.
 17. The method of claim 16, wherein a length of the first dummy gate electrode is greater than a sum of a length of the first gate electrode and a length of the third gate electrode.
 18. A method of forming an integrated circuit, the method comprising: forming a first cell, where forming the first cell comprises: forming a first fin in a PMOS region of the first cell; forming a second fin in the PMOS region of the first cell, the second fin extending in parallel with the first fin along a first direction; forming a first gate electrode over the first fin, the first gate electrode overlapping with an end of the second fin in a top view; forming a third fin in an NMOS region of the first cell; forming a fourth fin in the NMOS region of the first cell, the third fin and the fourth fin extending in parallel with the first fin; forming a second gate electrode over the third fin, the second gate electrode overlapping with an end of the fourth fin in the top view; and forming a first dummy gate electrode between the PMOS region and the NMOS region, the first dummy gate electrode extending in a second direction perpendicular to the first direction, wherein the first gate electrode and the second gate electrode are parallel with each other, and are disposed on opposing sides of the first dummy gate electrode.
 19. The method of claim 18, wherein forming the first dummy gate electrode comprises forming the first dummy gate electrode using an electrically conductive material.
 20. The method of claim 18, where forming the first cell further comprises forming a fifth fin in the PMOS region of the first cell, the fifth fin extending in the first direction, the first gate electrode extending over the first fin and over the fifth fin. 